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COMPRO X800 - START UP GUIDE Spezifikationen Seite 7

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Seitenansicht 6
_______________________________________________________________________________________ 7
MAX9249
Gigabit Multimedia Serial Link
Serializer with LVDS System Interface
Pin Description
Pin Configuration
RXIN1+
4
LVDSVDD
5
AGND
6
RXIN2-
7
RXIN2+
8
RXCLKIN-
9
RXCLKIN+
10
RXIN3-
11
RXIN3+
12
RXIN0-
1
RXIN0+
2
RXIN1-
3
33 32 31 30 29 28 27 26 2536 35 34
IOVDD
GND
DVDD
AGND
CNTL2
CNTL1
WS
SCK
SD/CNTL0
AVDD
LVDSVDD
AGND
IOVDD
GND
DVDD
N.C.
BWS
PWDN
CDS
MS
AUTOS
N.C.
AVDD
AGND
37
38
39
40
41
42
43
44
45
46
47
48
EP*
*EXPOSED PAD.
TOP VIEW
24
23
22
21
20
19
18
17
16
15
14
13
MAX9249
LMN0
AVDD
OUT+
OUT-
AGND
LMN1
SSEN
TX/SCL
RX/SDA
DRS
INT
LFLT
+
TQFP
PIN NAME FUNCTION
1–4, 7, 8,
11, 12
RXIN_-,
RXIN_+
Differential LVDS Data Inputs. Set BWS = low (3-channel mode) to use RXIN0_ to RXIN2_. Set
BWS = high (4-channel mode) to use RXIN0_ to RXIN3_.
5, 14 LVDSVDD
3.3V LVDS Power Supply. Bypass LVDSVDD to AGND with 0.1FF and 0.001FF capacitors as close
as possible to the device with the smaller value capacitor closest to LVDSVDD.
6, 13, 21,
29, 48
AGND Analog Ground
9, 10
RXCLKIN-,
RXCLKIN+
LVDS Input for the LVDS Clock
15, 32, 47 AVDD
1.8V Analog Power Supply. Bypass AVDD to AGND with 0.1FF and 0.001FF capacitors as close
as possible to the device with the smaller value capacitor closest to AVDD.
16 SD/CNTL0
I
2
S Serial-Data Input with Internal Pulldown to GND. Disable I
2
S to use SD/CNTL0 as an additional
input.
17 SCK I
2
S Serial-Clock Input with Internal Pulldown to GND
18 WS I
2
S Word-Select Input with Internal Pulldown to GND
19 CNTL1
Control Input 1 with Internal Pulldown to GND. Data is latched every RXCLKIN_ cycle (Figure 7).
CNTL1 is not available in 3-channel mode. Drive BWS high (4-channel mode) to use this input.
CNTL1 or RES (RES from VESA Standard Panel Specification) is mapped to DIN27 (see the
Reserved Bit (RES) section).
Seitenansicht 6
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